1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to I/O circuits.
2. Description of the Related Art
Typically, I/O circuits are responsible for communication between the integrated circuit and the outside world. These circuits may also perform power domain transfers e.g., transferring from a core power domain to an I/O power domain. Some system designs specify that upon a core power failure, the I/O signals have a predetermined state (i.e., low or high) at an integrated circuit output. Circuits that generate these predetermined states are known as power fail-safe circuits. The speed of systems including power fail-safe circuits are ever increasing, reducing associated circuit timing budgets. Thus, a need exists for a power fail-safe circuit design that introduces a reduced delay into a system including the power fail-safe circuit.